Discussion in "ARM Development" started by    shyam    Feb 7, 2008.
Thu Feb 07 2008, 07:03 AM
#1
please do not post on this thread for doubts post on

http://www.8051projects.net/forum-t5636-last.html


chapter 1 ARM Architecture
This chapter outlines the ARM processor's architecture and describes the syntax rules of the ARM
assembler. Later chapters describe the ARM's stack and exception processing system
in more detail.
Figure 1.1 on the following page shows the internal structure of the ARM processor. The ARM
is a Reduced Instruction Set Computer (RISC) system and includes the attributes typical to that
type of system:
• A large array of uniform registers.
• A load/store model of data-processing where operations can only operate on registers and not
directly on memory. This requires that all data be loaded into registers before an operation
can be preformed, the result can then be used for further processing or stored back into
memory.
• A small number of addressing modes with all load/store addresses begin determined from
registers and instruction elds only.
• A uniform xed length instruction (32-bit).
In addition to these traditional features of a RISC system the ARM provides a number of additional
features:
• Separate Arithmetic Logic Unit (ALU) and shifter giving additional control over data processing
to maximize execution speed.
• Auto-increment and Auto-decrement addressing modes to improve the operation of program
loops.
• Conditional execution of instructions to reduce pipeline ushing and thus increase execution
speed.







[ Edited Sat Feb 09 2008, 04:15 AM ]
 MATHIVANAN like this.
Thu Feb 07 2008, 07:58 AM
#2
1.1 Processor modes
The ARM supports the seven processor modes shown in table1.1.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing.
Most application programs execute in User mode. While the processor is in User mode, the
program being executed is unable to access some protected system resources or to change mode,
other than by causing an exception to occur (see 1.4 ). This allows a suitably written
operating system to control the use of system resources.
 MATHIVANAN like this.
Thu Feb 07 2008, 08:16 AM
#3
table1.1


[ Edited Thu Feb 07 2008, 08:57 AM ]
Thu Feb 07 2008, 10:05 AM
#4


The modes other than User mode are known as privileged modes. They have full access to system
resources and can change mode freely. Five of them are known as exception modes: FIQ (Fast
Interrupt), IRQ (Interrupt), Supervisor, Abort, and Undened. These are entered when specic
exceptions occur. Each of them has some additional registers to avoid corrupting User mode state
when the exception occurs (see 1.2 for details).
The remaining mode is System mode, it is not entered by any exception and has exactly the same
registers available as User mode. However, it is a privileged mode and is therefore not subject to
the User mode restrictions. It is intended for use by operating system tasks which need access to
system resources, but wish to avoid using the additional registers associated with the exception
modes. Avoiding such use ensures that the task state is not corrupted by the occurrence of any
exception.

Thu Feb 07 2008, 10:27 AM
#5


1.2 Registers
The ARM has a total of 37 registers. These comprise 30 general purpose registers, 6 status registers
and a program counter. Figure 1.2 illustrates the registers of the ARM. Only fteen of the general
purpose registers are available at any one time depending on the processor mode.
There are a standard set of eight general purpose registers that are always available (R0  R7) no
matter which mode the processor is in. These registers are truly general-purpose, with no special
uses being placed on them by the processors' architecture.
A few registers (R8  R12) are common to all processor modes with the exception of the q
mode. This means that to all intent and purpose these are general registers and have no special
use. However, when the processor is in the fast interrupt mode these registers and replaced with
dierent set of registers (R8_q - R12_q). Although the processor does not give any special
purpose to these registers they can be used to hold information between fast interrupts. You can
consider they to be static registers. The idea is that you can make a fast interrupt even faster
by holding information in these registers.
The general purpose registers can be used to handle 8-bit bytes, 16-bit half-words1, or 32-bit
words. When we use a 32-bit register in a byte instruction only the least signicant 8 bits are
used. In a half-word instruction only the least signicant 16 bits are used. Figure 3.3 demonstrates
this.
The remaining registers (R13  R15) are special purpose registers and have very specic roles:
R13 is also known as the Stack Pointer, while R14 is known as the Link Register, and R15 is
the Program Counter. The user (usr) and System (sys) modes share the same registers. The
exception modes all have their own version of these registers. Making a reference to register R14
will assume you are referring to the register for the current processor mode. If you wish to refer to the user mode version of this register you have refer to the R14_usr register. You may only
refer to register from other modes when the processor is in one of the privileged modes, i.e., any
mode other than user mode.
There are also one or two status registers depending on which mode the processor is in. The Current
Processor Status Register (CPSR) holds information about the current status of the processor
(including its current mode). In the exception modes there is an additional Saved Processor Status
Register (SPSR) which holds information on the processors state before the system changed into
this mode, i.e., the processor status just before an exception.



[ Edited Sat Feb 09 2008, 03:55 AM ]
Thu Feb 07 2008, 10:37 AM
#6
fig1.2
Sat Feb 09 2008, 03:58 AM
#7
1.2.1 The stack pointer, SP or R13
Register R13 is used as a stack pointer and is also known as the SP register. Each exception mode
has its own version of R13, which points to a stack dedicated to that exception mode.

1 .2.2 The Link Register, LR or R14
Register R14 is also known as the Link Register or LR.
It is used to hold the return address for a subroutine. When a subroutine call is performed via a
BL instruction, R14 is set to the address of the next instruction. To return from a subroutine you
need to copy the Link Register into the Program Counter. This is typically done in one of the two
ways:
• Execute either of these instructions:
MOV PC, LR or BAL LR
• On entry to the subroutine store R14 to the stack with an instruction of the form:
STMFD SP!,{hregistersi, LR}
and use a matching instruction to return from the subroutine:
LDMFD SP!,{hregistersi, PC}
This saves the Link Register on the stack at the start of the subroutine. On exit from the
subroutine it collects all the values it placed on the stack, including the return address that
was in the Link Register, except it returns this address directly into the Program Counter
instead.

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